1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus which does not have memory cells, and a testing method thereof.
2. Related Art
In order to improve the degree of integration of a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus, in which a plurality of chips are stacked and packaged in a single package, has been developed. Recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed in the art, in which through-silicon vias are formed to pass through a plurality of stacked chips such that all the memory chips are electrically coupled with one another.
Exemplifying memory apparatuses, two types of 3D semiconductor apparatuses may be configured. A first is a type in which a plurality of memory chips having substantially the same structure are stacked, and a second is a type in which at least two core chips each having a memory cell array and at least one base chip having no memory cell array are stacked.
Since the core chips have memory cells, the test of the core chips may be performed by storing data in the core chips or outputting stored data, through test equipment. However, since the base chip does not have a memory cell array, the reliability of the base chip may not be tested through input and output of data. Therefore, in the conventional art, the reliability of the base chip cannot help but be tested by performing a test for the entire 3D semiconductor apparatus after the base chip is stacked and packaged along with the core chips.